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VLSI circuit defect diagnosis: open defects and run-time speed

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Masthead Logo University of Iowa Iowa Research Online Theses and Dissertations 2008 VLSI circuit defect diagnosis: open defects and run-time speed Chen Liu University of Iowa Copyright 2008 Chen Liu This
Masthead Logo University of Iowa Iowa Research Online Theses and Dissertations 2008 VLSI circuit defect diagnosis: open defects and run-time speed Chen Liu University of Iowa Copyright 2008 Chen Liu This dissertation is available at Iowa Research Online: Recommended Citation Liu, Chen. VLSI circuit defect diagnosis: open defects and run-time speed. PhD (Doctor of Philosophy) thesis, University of Iowa, Follow this and additional works at: Part of the Electrical and Computer Engineering Commons VLSI CIRCUIT DEFECT DIAGNOSIS: OPEN DEFECTS AND RUN-TIME SPEED by Chen Liu An Abstract Of a thesis submitted in partial fulfillment of the requirements for the Doctor of Philosophy degree in Electrical and Computer Engineering in the Graduate College of The University of Iowa August 2008 Thesis Supervisor: Professor Sudhakar M. Reddy 1 ABSTRACT To shorten time-to-market of VLSI circuit chips, the yield must be ramped up by quickly discovering and rectifying the causes for systematic defects. Due to the shrinking feature size of devices 90nm and below, yield ramp up is becoming more and more difficult. Volume diagnosis with statistical learning is needed to cost effectively discover systematic defects. An accurate and high throughput diagnosis tool is required to diagnose large numbers of failing devices to aid statistical yield learning. In this work, we propose techniques to improve diagnosis accuracy and resolution, techniques to improve run-time performance. We consider the problem of determining the location of open defects in interconnects of deep submicron designs. We investigate a procedure that uses minimal information beyond the circuit net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure. A dictionary called N FB dictionary of small size and does not grow linearly with pattern count is proposed. It further reduced dictionary size over previous dictionary while still achieve higher failing pattern diagnosis performance than industry standard Effect-Cause diagnosis procedures. In this work we also propose a method to achieve higher speedup with a marginally larger dictionary than the N FB dictionary. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Hyperactive faults tend to propagate fault effects to many observation points and cost a large amount of time to simulate. 2 In addition to speed-up of failing pattern diagnosis, we propose a method to improve passing pattern performance. A pass-fail dictionary with high compression ratio is proposed. The dictionary is stored in a database on disk with a small cache memory and high diagnosis performance is demonstrated. Abstract Approved: Thesis Supervisor Title and Department Date VLSI CIRCUIT DEFECT DIAGNOSIS: OPEN DEFECTS AND RUN-TIME SPEED by Chen Liu A thesis submitted in partial fulfillment of the requirements for the Doctor of Philosophy degree in Electrical and Computer Engineering in the Graduate College of The University of Iowa August 2008 Thesis Supervisor: Professor Sudhakar M. Reddy Graduate College The University of Iowa Iowa City, Iowa CERTIFICATE OF APPROVAL PH.D. THESIS This is to certify that the Ph.D. thesis of Chen Liu has been approved by the Examining Committee for the thesis requirement for the Doctor of Philosophy degree in Electrical and Computer Engineering at the August 2008 graduation. Thesis Committee: Sudhakar M. Reddy, Thesis Supervisor Wu-Tung Cheng Jon G. Kuhl Sukumar Ghosh John P. Robinson Karl Lonngren To my family ii ACKNOWLEDGMENTS First and foremost, I would like to express my sincere gratitude to my academic advisor, Professor Sudhakar M. Reddy, for his excellent guidance and solid management throughout this research. Without his guidance, this work would not be even possible. Equal amount of thanks are given to Dr. Wu-Tung Cheng for his constructive advices and knowledgeable explanations. I also want to thank my committee members Prof. Kuhl, Prof. Zhang, Prof. Robinson, and Prof. Lonngren for serving on my committee and giving valuable suggestions. Mentor Graphics Corporation, Semiconductor Research Corporation (2007-TJ- 1642) provided a resourceful research environment and financial support. I hereby express my sincere appreciation. Many thanks to my friends and co-workers in my research: Huaxing Tang, Wei Zou, Manish Sharma, Chen Wang. I would like to thank my family for their understanding and encouragement. iii ABSTRACT To shorten time-to-market of VLSI circuit chips, the yield must be ramped up by quickly discovering and rectifying the causes for systematic defects. Due to the shrinking feature size of devices 90nm and below, yield ramp up is becoming more and more difficult. Volume diagnosis with statistical learning is needed to cost effectively discover systematic defects. An accurate and high throughput diagnosis tool is required to diagnose large numbers of failing devices to aid statistical yield learning. In this work, we propose techniques to improve diagnosis accuracy and resolution, techniques to improve run-time performance. We consider the problem of determining the location of open defects in interconnects of deep submicron designs. We investigate a procedure that uses minimal information beyond the circuit net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure. A dictionary called N FB dictionary of small size and does not grow linearly with pattern count is proposed. It further reduced dictionary size over previous dictionary while still achieve higher failing pattern diagnosis performance than industry standard Effect-Cause diagnosis procedures. In this work we also propose a method to achieve higher speedup with a marginally larger dictionary than the N FB dictionary. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Hyperactive faults tend to propagate fault effects to many observation points and cost a large amount of time to simulate. iv In addition to speed-up of failing pattern diagnosis, we propose a method to improve passing pattern performance. A pass-fail dictionary with high compression ratio is proposed. The dictionary is stored in a database on disk with a small cache memory and high diagnosis performance is demonstrated. v TABLE OF CONTENTS LIST OF TABLES... viii LIST OF FIGURES... ix CHAPTER 1. INTRODUCTION REVIEW OF DEFECT DIAGNOSIS ALGORITHMS Fault Models Cause-Effect Diagnosis Effect-Cause Diagnosis Single Location at a Time (SLAT) Multiple Fault Diagnosis Defect Diagnosis Using Open Fault Model Super Fault or Composite Stuck-at Open Fault Diagnosis Symbolic Simulation to Identify Open Defects Interconnect Open Diagnosis with Physical Information OPEN DEFECT DIAGNOSIS WITH MINIMAL PHYSICAL INFORMATION Introduction Preliminaries Review of Previous Works Overview of the Proposed Diagnosis Procedure Identifying Open Defects with Only Neighborhood Node List Information Identifying the Open Nets Using Logic Diagnosis Identifying the Open Segments Using Segment Fault Model Identifying Open Vias by Solving Inequalities Open Via Driving Multiple Gates...37 Experimental Results Discussion Conclusions IMPROVING DIAGNOSIS PERFORMANCE WITH MINIMAL MEMORY OVERHEAD Introduction Motivations Terminology Review of Effect-Cause Diagnosis Review of Cause-Effect Diagnosis Signature-Based Small Dictionary Proposed Techniques and Diagnosis Procedure N FB Dictionary FFR Grouping...57 vi 4.3.3 Proposed Algorithm Experimental Results Memory Overhead Event Reduction Run Time Speedup Conclusion INCREASED FAULT DIAGNOSIS THROUGHPUT USING DICTIONARY FOR HYPERACTIVE FAULTS Introduction Review of Previous Works Terminology Review of Cause-Effect Diagnosis Review of Effect-Cause Diagnosis Signature-based Small Dictionary N FB Dictionary Dictionaries for Hyperactive Faults Failing Bit Count Dictionary Hyperactive Faults Signature Dictionary Dictionary Sizes Flow of Diagnosis Procedure Using HF Dictionary Example of a Diagnosis Flow Experimental Results Conclusions PASSING PATTERN PERFORMANCE IMPROVEMENT Introduction Ideas on Passing Pattern Processing Speed Up Database for Pass-Fail Dictionary Pass-Fail Information Characteristics Review of Previous Works Frequency Directed Run-Length Codes (FDR) Golomb Codes Huffman Code Burrows-Wheeler Transformation Proposed Methods Experimental Results CONCLUSIONS REFERENCES vii LIST OF TABLES Table 1: Open Diagnosis Experiment Results...44 Table 2: Inaccurate Neighbor Capacitances...46 Table 3: Design Information and Dictionary Size...53 Table 4: FFR Grouping Faults...58 Table 5: Memory Overhead VS. Small Dictionary...64 Table 6: Information on Some Industrial Circuits Used in the Study...78 Table 7: Failing Bit Count (FBC) Dictionary...83 Table 8: Hyperactive Faults Signature (HFS) Dictionary...85 Table 9: Sizes (in MB) of Small Dictionary [37], NFB and HF Dictionaries...86 Table 10: Average Failing Pattern Process Time for Each Case in Seconds...92 Table 11: Information on Some Industrial Circuits Used in the Work...94 Table 12: Circuit Data for Pass Fail Information Characteristics Table 13: FDR Uni-Phase Coding Example Table 14: FDR Alternating Coding Example Table 15: Golomb Uni-Phase Coding Example Table 16: Burrows-Wheeler Transformation Table 17: Pass-Fail Dictionary Circuit Info Table 18: Pass-Fail Dictionary Experiment Data viii LIST OF FIGURES Figure 1: Flow of Diagnosis Procedure Using Effect-Cause Diagnosis...6 Figure 2: Byzantine Effect...17 Figure 3: Interconnect Open Model...20 Figure 4: A Net s Routing in the Layout...27 Figure 5: Interconnect Open Model...28 Figure 6: Circuit for Example Figure 7: Example of Via Driving Multiple Gates...38 Figure 8: Size of Small Dictionary for D Figure 9: Number of Failing Bit per Failing Pattern Distribution...56 Figure 10: Intersection of Critical Path Tracing...57 Figure 11: Fault Grouping Using FFR...58 Figure 12: Memory Overhead Without Fault Grouping...61 Figure 13: Memory Overhead With Fault Grouping...63 Figure 14: Reduction of the Number of Events...66 Figure 15: CPU Time Speedup (Failing Patterns)...67 Figure 16: Flow of Diagnosis Procedure Using Effect-Cause Diagnosis...74 Figure 17: Flow of Diagnosis Procedure Using Small Dictionary...76 Figure 18: Flow of Diagnosis Procedure Using N FB Dictionary...77 Figure 19: Distribution of the Number of Events...79 Figure 20: Hyperactive Fault Characteristics...80 Figure 21: Flow of Diagnosis Procedure Using N FB and HF Dictionaries...87 Figure 22: Diagnosis Time SpeedUp...90 Figure 23: Flow of Diagnosis Procedure Using Only HF Dictionary...91 Figure 24: Hyperactive Fault Dictionary Only Approach Speed Up...92 Figure 25: Diagnosis Time in Each Major Step...95 ix Figure 26: D1 Run of Zero Figure 27: D1 Run of One Figure 28: D6 Run of Zero Figure 29: D6 Run of One Figure 30: Example of a Huffman Tree x 1 CHAPTER 1. INTRODUCTION The purpose of fault diagnosis is to determine the cause of failure in a manufactured chip. To assist a designer or failure analysis engineer, the diagnosis tool tries to locate the possible positions of the failure effectively and quickly. The quality of a diagnosis impacts directly the time-to-market and the total product cost. Yield analysis can use diagnosis results of multiple failed devices to collect statistical data to identify yield limiting manufacture process issues or design errors. Due to the increasing difficulty of physical inspection for today s multi-layer deep sub-micron designs and the increasing cost of inspection equipments, logic diagnosis becomes a very important step in the process of silicon debug, yield ramp-up and field return analysis. We will briefly review the field of defect diagnosis. A state-of-the-art diagnosis tool should have the following properties: High diagnosis resolution: The number of candidate locations reported should be as small as possible. If the reported candidate set size is too large, the real defect will be hidden in vast number of false candidates and makes physical failure analysis extremely difficult. Cost of time and human power would be huge. High diagnosis accuracy: The set of candidate locations reported should be close to the set of real defects validated by physical analysis. Low accuracy wastes time and resources in physical failure analysis because the reported candidate set has low correlation with the real defects. High runtime efficiency: The speed of performing quality diagnosis should be high to facilitate volume diagnosis. With deep-submicron processes, especially 65nm design and below, systematic defects have become dominant. In order to catch systematic defects, a large volume of failed chips need to be diagnosed and the diagnosis results used for the statistical analysis. To diagnose a large number of failed chips in a reasonable time, the run time of diagnosis must be short. 2 The objective of diagnosis research is to improve diagnosis resolution and accuracy as well as improve diagnosis runtime performance. To make the research practical, the techniques developed were built on a commercial diagnosis tool and tested with real industrial designs. More realistic problems would be discovered by industrial circuits than small academic benchmarks. Following the introduction, we will briefly review previous works on the defect diagnosis in Chapter 2 and propose an open defect diagnosis technique in Chapter 3. In Chapter 4 we will propose a method of using dictionary to improve failing pattern diagnosis. In Chapter 5 we propose an additional dictionary to address the issue of hyperactive faults. In Chapter 6, a compressed database dictionary method to improve passing pattern diagnosis performance is proposed. Chapter 7 concludes the thesis. 3 CHAPTER 2. REVIEW OF DEFECT DIAGNOSIS ALGORITHMS In this chapter, we review current fault model based diagnosis techniques, including stuck fault model and open model. Also single fault diagnosis and multiple fault diagnosis are reviewed. 2.1 Fault Models We use fault models to model the effect of a defect for diagnosis. Currently logical fault models are widely used due to speed of simulation and simplicity. A logic fault model describes faulty behavior of a defect at the logic level. Model based defect diagnosis is a procedure to identity defects by using fault model simulations. Popular models are: stuck-at fault model, bridge fault model, open fault model, gate delay fault model and path delay fault model. Stuck-at fault model: Stuck-at is the simplest and most widely used model. Yet it effectively describes the behavior of a large portion of defects. In the stuck-at fault model, a node in the circuit always takes a fixed logic value, either 0 (stuck-at 0) or 1 (stuck-at 1). Stuck-at 0 could be the result of a short to the ground line. Stuck-at 1 could be the result of a short to the power supply line. Bridge fault model: The bridge fault model is used to describe logic behavior of two nodes that are shorted in the circuit. Common bridge fault models are: wired- AND/OR fault model, dominate fault model, 4-way bridge fault model. The wired- AND/OR bridge model assumes that the faulty node of the bridge always has the logic value 0(1). The dominate bridge model assumes that one node of the bridge always dominates the other node by imposing its logic value. Bridge model is a important model since bridging is a common defect in circuits. Open fault model: Open fault model attempts to model the open defects, such as electrical open, break, and disconnected via in a circuit. Opens can result in state-holding, intermittent, and pattern-dependent fault effects, thus open models are more complex. 4 Delay fault model: To represent timing related defects, gate delay model and path delay model are used. The gate delay model assumes the defect-induced delay is only between a single gate input and output. The path delay model spreads the total delay along a circuit path from a circuit input to a circuit output. Most diagnosis is based on stuck-at fault model. When we don t know what the defect category is, we first run stuck-at diagnosis. Base on the stuck-at diagnosis result, we can apply bridge and open model to determine whether the suspect is more like a bridge or open. There are two ways to use stuck-at fault model. One is the Effect-cause diagnosis that assumes there is a stuck-at fault and back trace from erroneous circuit outputs to find candidates, and then simulate the candidates to find the ones that best match the failure responses observed from the tester. The other is the Cause-effect diagnosis which uses a pre-simulated fault dictionary to lookup the failure response. 2.2 Cause-Effect Diagnosis A fault dictionary is a record of the errors that the modeled faults in the circuit are expected to cause [1]. It stores a mapping from the modeled fault to simulated response. The procedure of fault dictionary diagnosis is to look up the mapping table to find the suspect that is simulated to cause the faulty behavior. The fault candidate whose expected faulty signature matches best with the observed faulty signature will be chosen as the final fault candidate. If we assume a single stuck-at defect, there should be an exact match between the expected signature of the fault candidate and the observed faulty signature. There are several ways to store the signature information: a pass-fail dictionary, complete dictionary and compressed signature dictionary. The pass-fail dictionary only stores a single bit (pass or fail) of failure information for each fault per test pattern. Since it omits useful information of where the failing bits are, it renders distinguishing some 5 faults impossible. A complete dictionary is a full-response dictionary, which stores all circuit outputs in the presence of each fault for each test pattern. The number of bits required to store a complete dictionary equals F*V*O, where F is the number of faults, V is the number of test patterns, and O is the number of primary outputs. The downside of a complete dictionary is that the storage it requires is huge for designs with multi-million gates. The compressed signature dictionary is obtained by feeding the output information through a 32 or a 64 bit multiple input signature register (MISR) to get a compressed signature. There is the problem of aliasing, that two different output responses may be compressed to the same failure signature. But by choosing a MISR with more bits, the chance of aliasing is slim. The compressed signature dictionary saves storage space and provides about the same diagnosis resolution as the complete dictionary. In order to reduce the memory requirement for a complete dictionary, a number of procedures are proposed. In [2], dynamic creation, test set partitioning, and reduced fault lists are used to achieve a reduced fault dictionary. Pomeranz and Reddy [3] proposed a space compaction method that augments a pass-fail dictionary using a greedy algorithm to choose the primary outputs of some test patterns from a full response dictionary, which can distinguish the largest number of undistingu
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