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UNIVERSITY OF NAIROBI FINAL YEAR PROJECT DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING A FOUR QUADRANT CMOS ANALOGUE MULTIPLIER PROJECT NO: 001 By TAYABALI JUZER MURTAZAALI REG. NO: F17/39567/2011 SUPERVISOR: PROF. ELIJAH MWANGI EXAMINER: MR SAYYID A PROJECT REPORT SUBMITTED TO THE DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING IN PARTIAL FULFILLMENT OF THE REQUIREMENTS OF BSc. ELECTRICAL AND ELECTRONIC ENG. OF THE UNIVERSITY OF NAIROBI 16 th May, 2016 i DECLARATION OF ORIGINALITY FACULTY/ SCHOOL/ INSTITUTE: Engineering DEPARTMENT: Electrical and Information Engineering COURSE NAME: Bachelor of Science in Electrical & Electronic Engineering NAME OF STUDENT: JUZER MURTAZAALI TAYABALI REGISTRATION NUMBER: F17/39567/2011 COLLEGE: Architecture and Engineering WORK: A 4 QUADRANT CMOS ANALOGUE MULTIPLIER 1) I understand what plagiarism is and I am aware of the university policy in this regard. 2) I declare that this final year project report is my original work and has not been submitted elsewhere for examination, award of a degree or publication. Where other people s work or my own work has been used, this has properly been acknowledged and referenced in accordance with the University of Nairobi s requirements. 3) I have not sought or used the services of any professional agencies to produce this work. 4) I have not allowed, and shall not allow anyone to copy my work with the intention of passing it off as his/her own work. 5) I understand that any false claim in respect of this work shall result in disciplinary action, in accordance with University anti-plagiarism policy. Signature: Date: ii ACKNOWLEDGEMENT First and foremost, I wish to thank the God for guiding me and being by my side throughout my studies. I acknowledge the input by my supervisor, Prof. Elijah Mwangi, for the useful comments and suggestions which have led to the improvement of this project and for the guidance and moral support that he granted unto me during the development of this project. An assemblage of this nature could never have been attempted without reference to and inspiration from the works of others whose details are mentioned in reference section. I also acknowledge all of them. Last but not the least to all of my friends and classmates who were patiently extended all sorts of help for accomplishing this undertaking. iii ABSTRACT In this project, a four quadrant analogue multiplier based on the 0.18 micron CMOS technology has been presented. It is based on the square law characteristics of the MOS transistor drain current, operating in saturation. The multiplier design combines the features of both, the differential structure of the flipped voltage follower cell, and source follower. This design will improve the multiplier bandwidth by reducing the power dissipation, with low power supply. Simulation results are obtained using PSPICE 16.6 for 0.18μm CMOS process with supply voltage of 0.9Vdc. iv TABLE OF CONTENTS DECLARATION OF ORIGINALITY.. ii ACKNOWLEDGEMENT iii ABSTRACT iv TABLE OF CONTENTS v LIST OF FIGURES....viii LIST OF TABLES... ix LIST OF ABBREVIATIONS ANDACRONYMS x 1 CHAPTER 1- INTRODUCTION BACKGROUND: PROBLEM STATEMENT OBJECTIVES PROJECT SCOPE CHAPTER 2-LITERATURE REVIEW INTRODUCTION STRUCTURE AND PHYSICAL OPERATION OF THE ENHANCEMENT-TYPE MOSFET [1] DEVICE STRUCTURE OPERATION OF A MOSFET [1] OPERATION WITH ZERO GATE VOLTAGE OPERATION WITH A GATE VOLTAGE ONLY APPLYING A SMALL V DS OPERATION AS V DS IS INCREASED v 2.3 DERIVATION OF THE I D -V DS RELATIONSHIP COMPLEMENTARY MOS OR CMOS THE DEPLETION-TYPE MOSFET [1] PREVIOUS PROJECTS CHAPTER 3-METHODOLOGY AND DESIGN INTRODUCTION SOURCE FOLLOWER FVF DIFFERENTIAL STRUCTURE (DFVF) THE COMPLETE MULTIPLIER TRANSISTOR PARAMETERS [4] CHAPTER 4- COMPUTER SIMULATION RESULTS INTRODUTION BIAS POINT ANALYSIS DC TRANSFER CHARACTERISTICS TRANSIENT ANALYSIS PSPICE COMMAND FILE DISCUSSION HAND CALCULATIONS COMPUTER SIMULATION RESULTS CHAPTER 5-CONCLUSION AND RECOMMENDATION vi 5.1 CONCLUSION RECOMMENDATION REFERENCES vii LIST OF FIGURES FIGURE 1-1: BLOCK DIAGRAM OF MULTIPLIER OPERATION... 1 FIGURE 2-1: PHYSICAL STRUCTURE OF THE ENHANCEMENT-TYPE NMOS TRANSISTOR: (A) PERSPECTIVE VIEW; (B) CROSS-SECTION FIGURE 2-2: (A) CIRCUIT SYMBOL FOR THE N-CHANNEL ENHANCEMENT-TYPE MOSFET. (B) MODIFIED CIRCUIT SYMBOL (C) SIMPLIFIED CIRCUIT SYMBOL... 6 FIGURE 2-3: OPERATION WITH ZERO GATE VOLTAGE... 7 FIGURE 2-4: OPERATION WITH A GATE VOLTAGE ONLY... 8 FIGURE 2-5: ATTRACTION OF ELECTRONS FROM THE N+ SOURCE AND DRAIN REGIONS INTO THE CHANNEL FIGURE 2-6: FORMATION OF AN N-CHANNEL BETWEEN THE SOURCE AND THE DRAIN REGIONS FIGURE 2-7: AN NMOS TRANSISTOR WITH V GS V T AND WITH A SMALL V DS APPLIED FIGURE 2-8: I D V DS CHARACTERISTICS OF THE NMOS FIGURE 2-9: OPERATION AS V DS IS INCREASED FIGURE 2-10: I D VERSUS V DS FOR AN FIGURE 2-11: DERIVATION OF THE I D V DS FIGURE 2-12: CROSS-SECTION OF A CMOS INTEGRATED CIRCUIT FIGURE 2-13: CIRCUIT SYMBOL FOR AN N-CHANNEL DEPLETION MOSFET FIGURE 2-14: DEPLETION NMOS TRANSISTOR WITH CURRENT AND VOLTAGE POLARITIES INDICATED FIGURE 2-15: I D V DS CHARACTERISTICS FOR A DEPLETION NMOS FIGURE 2-16: THE RELATIVE LEVELS OF TERMINAL VOLTAGES OF A DEPLETION- TYPE FIGURE 2-17: THE I D V GS CHARACTERISTIC IN SATURATION FIGURE 2-18: 45NM MODEL PARAMETERS FIGURE 3-1: SCHEMATIC OF THE SOURCE FOLLOWER CIRCUIT FIGURE 3-2: SCHEMATIC OF THE FVF DIFFERENTIAL STRUCTURE CIRCUIT FIGURE 3-3: THE COMPLETE FOUR QUADRANT MULTIPLIER CIRCUIT FIGURE 3-4: PSPICE MODEL EDITOR FOR NMOS FIGURE 4-1: BIAS VOLTAGES FIGURE 4-2: BIAS CURRENTS FIGURE 4-3: DC TRANSFER CHARACTERISTICS FIGURE 4-4: TRANSIENT ANALYSIS FIGURE 4-5: INPUT AND OUTPUT WAVEFORMS viii LIST OF TABLES TABLE 1-1: TYPES OF MULTIPLIERS, THEIR INPUT AND OUTPUT RANGE 1 TABLE 3-1: LENGTHS AND WIDTHS FOR TRANSISTORS TABLE 3-2: VALUES OF DIFFERENT CIRCUIT PARAMETERS TABLE 3-3: 0.18µ MOSFET MODEL PARAMETER ix LIST OF ABBREVIATIONS AND ACRONYMS MOSFET- METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR NMOS- N-CHANNEL METAL OXIDE SEMICONDUTOR PMOS- P-CHANNEL METAL OXIDE SEMICONDUCTOR FET- FIELD EFFET TRANSISTOR JFET- JUNCTION FIELD EFFECT TRANSISTOR PSPICE- PERSONAL COMPURER SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS. BJT- BIPOLAR JUNCTION TRANSISTOR FVF-FLIPPED VOLTAGE FOLLOWER V C - COMMON MODE VOLTAGE V DS -DRAIN TO SOURCE VOLTAGE V GS -GATE TO SOURE VOLTAGE V t -THRESHOLD VOLTAGE W- WIDTH L- LENGTH V DD - DC DRIVING VOLTAGE g/k - TRANSCONDUCTANCE V Dsat - SATURATION DRAIN VOLTAGE IC INTEGRATED CIRCUIT I CURRENT V VOLTAGE R RESISTANCE x xi 12 1 CHAPTER 1- INTRODUCTION 1.1 BACKGROUND: An analog multiplier is a device having two input ports and an output port. The signal at the output is the product of the two input signals. If both input and output signals are voltages, the transfer characteristic is the product of the two voltages multiplied by a scaling factor, K, as shown below in figure 1.1, which has the dimension of voltage. Typical types of different multiplier realizations have been shown in the table 1.1 below. Table 1-1 type of multipliers, their input range and output range TYPE V X V Y V OUT SINGLE QUADRANT UNIPOLAR UNIPOLAR UNIPOLAR TWO QUADRANT BIPOLAR UNIPOLAR BIPOLAR FOUR QUADRANT BIPOLAR BIPOLAR BIPOLAR V 1 V 2 V out =K *V 1 *V 2 K=CONSTANT Figure 1-1: Block diagram of multiplier operation From a mathematical point of view, multiplication is a four quadrant operation that is to say that both inputs may be either positive or negative, as may be the output. Some of the circuits used to produce electronic multipliers, however, are limited to signals of one polarity. If both signals must be unipolar, we have a single quadrant multiplier, and the output will also be 1 unipolar. If one of the signals is unipolar, but the other may have either polarity, the multiplier is a two quadrant multiplier, and the output may have either polarity (and is bipolar ). All the types of the multiplier have been shown in table 1 above. 4 quadrant multiplier is a very useful building block in many circuits such as adaptive filters, frequency shifters and modulators. These applications are required to operate in low voltage environment for improving their power efficiency and incorporating with mixed signal systems to be used in portable applications. In this project, I have discussed a 4 quadrant analog multiplier circuit which is based on CMOS technology. This multiplier relies on the quadratic drain current/gate voltage characteristics of MOS transistors operating in saturation. The design has been simulated in SPICE simulating software-pspice by using model parameter 0.18 micron technology CMOS process. 2 1.2 PROBLEM STATEMENT Recently only a few CMOS multiplier designs have been proposed. To bridge this gap and to familiarize with designs related to MOS technology the following project has been realized. 1.3 OBJECTIVES The project has the following objectives; 1. To investigate a CMOS 4 quadrant analogue multiplier 2. To familiarize with the pspice simulation software. 3. To make comparison between simulation and paper and pencil calculations. 1.4 PROJECT SCOPE This project entails the following; Developing a circuitry that shows the implementation of a 4 quadrant multiplier realized in CMOS technology. Simulating the design in PSPISE to verify the calculations done by hand. 3 2 CHAPTER 2-LITERATURE REVIEW 2.1 INTRODUCTION The FET (field effect transistors) is another type of transistors in the family of transistors. We have the BJT as one type and the FET as the other. The FET is further divided into the MOSFET,JFET and the MESFET. Although the basic concept of the FET has been known since the 1930s, the device became a practical reality only in the 1960s. Since the late 1970s, a particular kind of FET, the metal oxide semiconductor field effect transistor (MOSFET), has been extremely popular [1]. Compared to the BJTs, MOS transistors can be made quite small (that is, occupying a small silicon area on the IC chip), and there, manufacturing process is relatively simple. Furthermore, digital logic and memory functions can be implemented with circuits that use only MOSFETs. For these reasons, most very large scale integrated (VLSI) circuits are made at the present time using MOS technology. Examples include microprocessor and memory chips. MOS technology has also been applied extensively in the design of analog integrated circuits and in integrated circuits that combine both analog and digital circuits. There are two types of MOSFETs; 1. Enhancement type 2. Depletion type 4 2.2 STRUCTURE AND PHYSICAL OPERATION OF THE ENHANCEMENT-TYPE MOSFET [1] The enhancement type MOSFET is the most widely used field effect transistor. In the discussion below its structure and physical operation is discussed. Also its current voltage characteristics will be discussed DEVICE STRUCTURE The figure 2.1 below shows the physical structure of the n-channel enhancement type MOSFET. The transistor is fabricated on a p-type substrate, which is a single crystal silicon wafer that provides physical support for the device. Two heavily doped n-type regions,indicated in the figure as the n + source and n + drain regions, are created in the substrate. A thin (0.02 to 0.1µm) layer of silicon dioxide (SiO 2 ), which is an excellent electrical insulator, is grown on the surface of the substrate, covering the area between the source and drain regions. Metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are also made to the source region, the drain region, and the substrate, also known as the body. Thus 4 terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or body terminal (B). Figure 2-1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. 5 Figure 2-2: (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol (c) Simplified circuit symbol From the figure 2.1(b) it is also observed that the substrate forms p-n junctions with the source and drain regions. In normal operations, these p-n junctions are kept reversed biased at all times. Since the drain will be at a positive voltage relative to the source, the two p-n junctions can be effectively cut-off, by simply connecting the substrate terminal to the source terminal. Thus, here, the substrate will be considered as having no operation on the device operation, and the MOSFET will be treated as a three terminal device, having gate(g), source(s), and drain(d). Note: we shall assume this to be the case in all our descriptions of NMOS, and substrate terminal connected to dc drive voltage (V dd ) for all PMOS. 6 2.2.2 OPERATION OF A MOSFET [1] Operation with zero gate voltage With zero voltage applied to gate, two back-to-back diodes exist in series between drain and source as shown in the figure 2.3 below. They prevent current conduction from drain to source when a voltage V DS is applied, yielding very high resistance (10 12 Ω) Figure 2-3: Operation with zero gate voltage Operation with a gate voltage only Here we ground the source and the drain, and apply a voltage at the gate terminal with respect to the source which is at ground potential, hence the name V GS. The positive voltage on the gate causes a positive build-up of positive charge along the metal electrode. This build up causes free holes to be repelled from region of p-type substrate under gate as shown in the figure 2.4 below. 7 Figure 2-4: Operation with a gate voltage only This migration results in the uncovering of negative bound charges, originally neutralized by the free holes. The positive gate voltage also attracts electrons from the n+ source and drain regions into the channel as shown in figure 2.5 below. 8 Figure 2-5: Attraction of electrons from the n+ source and drain regions into the channel. Once a sufficient number of these electrons accumulate, an n-region is created connecting the source and drain regions. This provides path for current flow between D and S, as shown in the figure 2.6 below. 9 this induced channel is also known as an inversion layer Figure 2-6: formation of an n-channel between the source and the drain regions. Correspondingly, the MOSFET in the figure 2.6 shown above is called an n-channel MOSFET or, alternatively, NMOS transistor. Note that an n-channel MOSFET is formed in a p-type substrate: the channel is created by inverting the substrate surface from p-type to n-type. Hence the induced channel is also called an inversion layer. The value of V GS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted V t. Obviously, 10 V t for an n-channel FET is positive. The value of V t is controlled during device fabrication and typically lies in the range 1V to 3V. A p-channel enhancement type MOSFET (PMOS) is fabricated on an n-type substrate with p + regions for the drain and source, and has holes as charge carriers. The device operates in the same manner as the n-channel device except that V GS and V DS are negative and the threshold voltage V t is negative. Also, the current i D enters the source terminal and leaves through the drain terminal. The gate and body of the MOSFET form a parallel plate capacitor with the oxide layer acting as the capacitor dielectric. The positive gate voltage causes positive charge to accumulate on the top plate of the capacitor (the gate electrode). The corresponding negative charge on the bottom plate is formed by the electrons in the induced channel. An electric field thus develops in the vertical direction. It is this field that controls the amount of charge in the channel, and thus determines the channel conductivity and, in turn, the current that will flow through the channel when a voltage V DS is applied Applying a small VDS Having induced a channel, we now apply a positive voltage V DS between drain and source, as shown in the figure 2.7 below. The voltage V DS causes a current i D to flow through the induced n channel. Current is carried by free electrons travelling from source to drain. The magnitude of i D depends on the density of electrons in the channel, which in turn depends on the magnitude of V GS. Specifically as V GS =V t the channel is just induced and the current conducted is still negligibly small. As V GS exceeds V t, more electrons are attracted into the channel. We may visualize the increase in charge carriers in the channel as an increase in channel depth. The result is a channel of increased conductance or, reduced resistance. In fact, the conductance of the channel is proportional to the excess gate voltage (V GS -V t ) also known as effective voltage, or overdrive voltage. It follows that the current i D will be proportional to (V GS -V t ) and, of course, to the voltage V DS that causes i D to flow. 11 Figure 2-7: An NMOS transistor with V GS V t and with a small V DS applied The figure 2.8 below shows a sketch of i D verses V DS for various values of V GS. It is observed that the MOSFET is operating as a linear resistance whose value is controlled by VGS. The resistance is infinite for V GS V t, and its value decreases as V GS exceeds V t. The description above indicates that for the MOSFET to conduct, a channel has to be induced. Then, increasing V GS above the threshold voltage V t enhances the channel; hence the name enhancement-mode operation and enhancement type MOSFET. Finally, we note that the current that leaves the source (i S ) is equal to the current that enters the drain terminal (i D ), and the gate current i G =0. 12 Figure 2-8: i D V DS characteristics of the NMOS 13 OPERATION AS VDS IS INCREASED Figure 2-9: Operation as V DS is increased. For this section V GS is held constant at a value greater than V t, as V DS is increased. The voltage between the gate and the points along the channel decreases from V GS at the source end to V GS - V DS at the drain end. Since the channel depth depends on this voltage, we find that the channel is no longer of uniform depth; rather the channel will take the tapered form as shown in the figure 2.9 above being deepest at the source end and shallowest at the drain end. As V DS is increased, the channel becomes more tapered and its resistance increases correspondingly. Thus the i D -V DS curve does not continue as a straight line but bends as shown in figure 2.10 below. Eventually, when V DS is increased to the value that reduces the voltage between the gate and channel at the drain end to V t : that is, V GS -V DS =V t or V DS =V GS -V t ; the channel depth at the drain end decreases 14 to almost zero, and the channel is said to be pinched off. Increasing V DS beyond this point has no effect to the channel shape, and the current remains constant. The drain current thus saturates at this value, and the MOSFET is said to have entered the saturation region of operation. The voltage V DS at which saturation occurs is denoted V DSsat,..(2.1) The region of the i D -V DS characteristic obtained for V DS V DSsat is called the triode region. Figure 2-10: i D versus V DS for an NMOS transistor operated with V GS V t. 2.3 DERIVATION OF THE ID-VDS RELATIONSHIP The above description can be used to derive an expression for the i D -V DS relationship depicted in the figure 2.10 above 15 Assuming that a voltage V GS is applied between gate and source with V GS Vt, and a voltage V DS is applied between drain and source. First considering operation in the triode region; that is, let V DS V GS -Vt. The channel will have the tapered shape as shown in figure 2.11 below. Consider an infinitesimal portion of the channel of length dx at a point x from the source, and let the voltage at this point be V(x). The voltage between gate and this point in the channel, [V GS - V(x)], obviously must be greater than the threshold voltage Vt, and the elec
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