Group No-01_low Power Fpga Design

LOW POWER FPGA DESIGN Neville Dsouza, Melwin Poovakottu, Rubin Stephen, Bradley Quadros Department of Electronics and Telecommunication Engineering, DON BOSCO INSTITUTE OF TECHNOLOGY Abstract— A complete system for the implementation of digital logic in a FieldProgrammable Gate Array (FPGA) platform is introduced. The variety of novel power-efficient FPGA architecture was designed and simulated in STM 0.130 μm Cmos technology. The detailed design and circuit characteristics of the Configurable
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  LOW POWER FPGA DESIGN Neville Dsouza, Melwin Poovakottu, Rubin Stephen,   Bradley Quadros Department of Electronics and Telecommunication Engineering,DON BOSCO INSTITUTE OF TECHNOLO!  Abstract  —      complete s#stem for t$e implementation of digital logic in a Field%&rogramma'le ate rra# (F& ) platform is introduced* T$e +ariet# of no+el poer%efficient F& arc$itecture as designed and simulated in ST- .*/0. 1m Cmos tec$nolog#* T$e detailed design and circuit c$aracteristics of t$e Configura'le Logic Bloc2 ere determined and e+aluated in terms of energ#, dela# and area* num'er of circuit%le+el lo%poer tec$ni3ues ere emplo#ed 'ecause poer consumption as t$e  primar# concern* Keywords: FPGA, circuit design, CAD tools   Introduction  In the 90-nm era and beyond, the number of transistors on a chip surmounts one billion and the development cost and time have been increasing rapidly. One solution for this problem is to use a reconfigurable LSI such as an F! #field  programmable gate arrays$, %hich is attractive #&'($ cost and short time-to-mar)et *+. Since an F! uses more transistors per function than So #system-on-a-chip$ to achieve programmability,  po%er consumption, es-pecially the lea)age po%er of an F! is larger than that of an So. F! s have recently benefited from technology process advances to become a significant alternative to pplication Specific Integrated ircuits # SIs$. n important feature that has made F! s, particularly attractive is that the logic mapping and implementation flo% is similar to the SI design flo% #from /L or erilog do%n to the configuration bitstream$  provided by the industrial sector. /o%ever, in order to implement real-life applications on an F! platform, embedded or discrete, increasingly performance and po%er-efficient F! architectures are re1uired.Furthermore, efficient architectures cannot be used effectively %ithout a complete set of tools for implementing logic %hile utili2ing the advantages and features of the target device Field-rogrammable !ate rrays #F! 3s$ are pre-fabricated silicon devices that can be electrically programmed to become almost any )ind of digitalcircuit or system. 4hey provide a number of compelling advantages over fi5ed-function pplication Specific Integrated ircuit# SI$technologies such as standard cells SI3stypically ta)e months to fabricate and costhundreds of thousands to millions of dollars toobtain the first device6 F! 3s are configured inless than a second #and can often be reconfigured if a mista)e is made$ and cost any%here from a fe%dollars to a fe% thousand dollars. 4he fle5iblenature of an F! comes at a significant cost inarea, delay, and po%er consumption.   1. FPGA ARCHITECURE F! 3s, as illustrated in Figure, consist of an array of programmable Logic bloc)s of potentially different types, including general Logic, memory and multiplier bloc)s, surrounded by a  programmable'outing fabric that allo%s bloc)s to be  programmable interconnected. 4he array is surrounded by programmable input7output bloc)s, labelled I7O in the figure that connects the chip to the outside %orld. 4he 8programmable term in F! indicates ability to program  function into the chip after silicon fabrication is complete. 4his customi2ation is made possible by the programming technology, %hich is method that can cause a change in the behavior of the pre-fabricatedhip after fabrication, in the 8field, %here system users create designs.   Fig.1  FPGA Architecture Basic Arcit!ctur! :ost of the today;s F! 3s are categori2ed as island-style F! 3s. n island-style F! is a t%odimensional array of logic bloc)s surrounded by I7O cells on its sides. 4hese logic bloc)s and I7O cells are all interconnected using a programmable routing architecture. In order to improve the  performance of F! 3s, most of the commercial F! 3s also include hard bloc)s %ith fi5ed functionality %hich offer faster, more compact implementations of hard%are functions than synthesis on the general logic of an F! . (5ample of such hard bloc)s is S' :s and multipliers.  Fig.1  illustrates such architecture. LUT In uts #$%. 4he L<4 is used for the implementationof logic functions. It has been demonstrated in that a =-input L<4 lead to the lo%est po%er consumption for theF! , providing an efficient area-delay product *+. C&ust!r Si'! #N%. 4he luster Si2e corresponds to the number of >L(s %ithin a L>. 4a)ing into account mostly the minimi2ation of po%er consumption, our design e5ploration proved that a cluster si2e of ? >L(s leads to the minimi2ation of po%er consumption *+.   Fig. 2.a  Basic Logic Element  Fig.2.b Logic Cluster   Lo(ic B&oc)s  Lookup-Tables (LUT’s) can be used to store truth table implementations of logic functions. >y storing the proper bits in the L<43s, various combinational logic functions could be implemented. 4o be able to implement se1uential circuits li)e FS:3s, a register is connected to the output of L<43s. 4his structures %hich is sho%n above is called a  Logic Element (LE) or  Basic  Logic Element (BLE) .  reviously, it is sho%n that =-input L<4s give the  best rea-elay compromise in F! s *+.   *. POWER CONSU+PTION Sourc!s o, o-!r consu tion : 4he three main sources of po%er consumption are inrush, standby and dynamic. urrent associated %ith the po%er-up se1uence of a device is referred to as inrush current. Standby po%er, also )no%n as static po%er, is the po%er of a device %hen the  po%er lines are active and %hen there is no s%itching activity on the I7Os. ynamic po%er, also referred to as   s%itching po%er, is the po%er associated %ith a device during normal operation.Inrush current is device-specific. For e5ample, S' :-based F! s have a high inrush current  because on po%er-up these devices are not configured and need to actively do%nload data from e5ternal memory chips to configure their  programmable resources, such as routing connections and loo)up tables. onversely, anti-fuse-based F! s do not have a high inrush current since they do not re1uire po%er-on configuration.:uch li)e inrush po%er, standby po%er depends heavily on the electrical characteristics of a component. ue to the e5tensive number of S' :cells %ithin S' : F! interconnects, they can consume hundreds of milliamps even at standby. Since anti-fuse F! s have metal-to-metal interconnects, they do not re1uire the additional transistors, and hence po%er, to retain interconnects. /o%ever, for both F! process types, lea)age current increases as process geometry shrin)s, %hich e5acerbates the po%er  problem. s an additional dilemma, dynamic po%er can easily be several times greater than standby po%er. ynamic po%er is proportional to the fre1uency of charging and discharging of internal parasitic capacitances of a component, such as registers and combinatorial logic, so optimi2ations are generally design-oriented. Cuttin( o-!r consu tion @4he follo%ing are some techni1ues that can  be used to minimi2e po%er consumption %ithin an F! design@ ã Voltage Switching:  Pavg = Cload  !dd   clk  4he above e1uation sho%s that the average s%itching po%er dissipation is proportional to the s1uare of the po%er supply voltage6 hence, reduction of dd %ill significantly reduce the  po%er consumption *A. /. LOW POWER I+PLE+ENTATION ã Gat!d C&oc) Si(na&s  : 4he s%itching po%er dissipation in the cloc) distribution net%or) can be very significant. If certain logic bloc)s in a system are not immediately used during the current cloc) cycle, temporarily disabling the cloc) signals of these bloc)s %ill obviously save s%itching  po%er. 4emporarily unused modules can have their cloc)s slo%ed or stopped. o%er savings comes from cloc)s only being provided to certain portions of the design at any given time.!ating a cloc) contributes to a significant amount of po%er savings because the number of active cloc) buffers reduces the number of toggling flip-flops decreases, and conse1uently the fan-out of those flip-flops %ill be less li)elyto toggle. !ating cloc)s re1uires careful  planning and partitioning of algorithms, but the  po%er savings can be considerable *A.  dding latches at the inputs of largecombinatorial logic #e.g., %ide bus multiple5er$  can suppress invalid s%itching activity, becauseinputs are latched only %hen the outputs aresupposed to be updated. Similarly, control registerscan be implemented to enable or disable lo%er-level modules #e.g., state machines in submodules$. /olding large buses and sub modules ina constant state helps reduce the amount of irrelevant s%itching. !ated cloc) at >L( levelsaves upto BBC of po%er *+.  0. ADANTAGES OF FPGA n F! is similar to several other types of devices %hich have been around for 1uite a %hile, the difference being that an F! is simply much more e5pandable and versatile. 4he devices %hich F! s get compared to most often are Ls #omple5 rogrammable Logic evices$, %hich are similar in function but typically have %ay less logic gates inside them6 ustomi2able < design is much more feasible %ith an F! . Once upon a time, L3s also   had the distinct advantage of retaining their configuration %hen turned off6 Dhen F! 3s first came out, they used simple S' : to hold their configuration, %hich of course%ould be lost %hen the device lost po%er. >ac) then, the F! had to be programmed from scratch every time it %as turned on, usually from a separate serial 'O: chip. >ut today, F! 3s comein Flash, ('O:, and (('O: variants, %hich %ill retain configuration, and %hich can also be re- programmed. #Fuse and anti-fuse F! 3s also e5ist, %hich act li)e 'O:3s in that they are one-time programmable, and cannot be reprogrammed after%ard.$ espite this, ho%ever, most F! 3s still use S' : for reasons of simplicity #%hen youneed to reprogram it, it;s easier to re-encode a small'O: chip than to reprogram a large F! chip$, so count on having to use a separate boot 'O: for the F! . <se of an F! is broadly divided into t%o main stages@ 4he first is Econfiguration modeE, the mode in %hich the F! is %hen you first po%er it up. onfiguration mode is, as you may have guessed, %here you configure the F! 6 4hat is, this is %hen you load your code into it, dictating ho% the  pins behave. Once configuration is complete, the F! goes into Euser modeE, its main mode of operation, %here the programmed circuit actually starts functioning. Conc&usions n effective F! bloc) is designed %ithimplementation of lo% po%er techni1ue, and is alsoverified for different combinational logics. A C$NOWLEDG+ENT roect is team%or) and reflects the contributionof many people. De %ould li)e to than) everyone %ho has contributed to this effort bysharing their time and ta)ing interest in our %or) and encouraging us all the %ay through. R!,!r!nc!s +.I((( paper on 8 &ovel F! rchitecture and an Integrated Frame%or) of     .A.:OS igital Integrated ircuits >y Sung-:oGang and Husuf Leblebici,.'.. Llopis and :. Sachdev, 8Lo% po%er,testable dual edge triggered ip- ops, roc.I((( International Symposium on Lo% o%er (lectronics and esign, :onterey, <S , ug.  
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