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SILICON DRIFT DETECTORS AND TIME PROJECTION CHAMBERS READOUTS WITH ON-LINE PROCESSING USING FAST VLSI DEDICATED FUZZY PROCESSORS

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SILICON DRIFT DETECTORS AND TIME PROJECTION CHAMBERS READOUTS WITH ON-LINE PROCESSING USING FAST VLSI DEDICATED FUZZY PROCESSORS G. V. Russo, D. Lo Presti, S. Panebianco, C. Petta, N. Randazzo, S. Reito
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SILICON DRIFT DETECTORS AND TIME PROJECTION CHAMBERS READOUTS WITH ON-LINE PROCESSING USING FAST VLSI DEDICATED FUZZY PROCESSORS G. V. Russo, D. Lo Presti, S. Panebianco, C. Petta, N. Randazzo, S. Reito Dipartimento di Fisica dell Università and Sezione INFN, Catania, Italy M. Russo Istituto di Ing. El. e Telecom. dell Università and Sezione INFN, Catania, Italy C. Caligiore Centro Siciliano di Fisica Nucleare e Struttura della Materia and Sezione INFN, Catania, Italy M. M. Masetti, E. Gandolfi, A.Gabrielli Dipartimento di Fisica dell Università and Sezione INFN, Bologna, Italy Talk has been given by N. Randazzo Abstract A smart solution concerning the Front End (F.E.) and the readout of Silicon Drift Chamber or Time Projection Chamber too is proposed. It foresees On- Line Data Processing to reduce meaningfully the number of wires inside the detector itself and toward acquisition system, especially salient in ALICE detector. Besides it produces a significant decrease of the transmitted data without loosing essential informations too. A central role plays a Processor that exploiting Fuzzy Logic is capable to compute, with a reasonable precision, the position of the tracks and the total charge released inside the detector. Using an ON-Line calibration tool it is possible to correct detector characteristics' dispersions and its temperature drift. 1. Introduction In the present paper we illustrate some applications of Fuzzy Logic to detectors like Silicon Drift Detector (SDD) or Time Projection Chamber (TPC) used in High Energy Physics (HEP). Fuzzy Logic can help us to solve brilliantly many problems: a big number of channel to read; high rate; ON-LINE data decoding and compressing; noise immunity; thermal drift; detector characteristics' dispersions. Besides it will be possible to put detectors, F.E. and Readout closer and to reduce cabling. A very preliminary version of this proposal applied to SDDs was already presented [1] - [2]. An extension to TPC is straightforward because of lower speed of its signals. The huge amount of data incoming from this type of detectors in LHC requires at least a zero suppression system. Different solutions have been proposed [3]. All of them foresee preamplification and analog data storage. Same kind of sparse readout or threshold must be foreseen. Let us suppose to know the preamplifier impulse response and the shapes of signals outgoing from the detectors. If we use an appropriate method of centreof-mass we can compute the position of the hit and the total charge released with a good precision. We would execute ON-LINE this computation, with a simple Fuzzy Processor (FP), not expensive but very fast. It can be put far from the detector in such a way to decrease cabling, power dissipation and matter. In Alice Pb+Pb reaction at LHC, the two layers of SDDs produce about 432 Mbit/event, in the worst case, if any compression method is not used. With a simple zero suppression one may go up to 9 Mbit/event. Using an FP ON-LINE one may obtain a further compression up to 1.1 Mb/event. 2. The overall system The schematic diagram of the electronics proposed for the readout of SDDs is shown in Fig.1. Each ½ detector has 384 anodes. It is connected to input Transimpedance Amplifiers (TAs). Each of these TAs drives a 32-channels Event Memory Chip (EMC). Twelve EMCs form the Event Memory (EM) able to store all data originating from ½ detector. The EM contains two memories, each of them looks like a 384x256-cells matrix. The Analog Memory (AM), stores analogue data, the Mirror Memory (MM) stores binary data. The signals coming from the TAs are continuously sampled at 40 MHz. The samplings are stored in the cells of the AM. One has the temporal evolution of the signal on the X-th anode in the 256 cells with the same index X. The 384 cells with the same index T contain the spatial evolution of the signals on the anodes at time T. The contigous entries in the EM, coming from the charge released by a particle, form a cluster. To detect a cluster we check a set of 5 analog data, forming a 384 Detector wires TA Channel Transimpedance Amplifier 384 EM Channel 9 bit wires 1 wire 9 wires Event ADC Memory FP 10 Input 4 Output Fuzzy Processor OMB 36 x 220 Output Memory Buffer Output Bus IR Inference RAM CU Control Unit Ready Tr Read Set Rules Fig.1. Front End and readout system schematic cross in the AM, to see if the cross central entry containing the highest value. To this aim, while data enter in the EM, they are processed by a circuit, that looks for clusters, that is the Cluster Finder (CF). When it detects a cluster, having a peak in the position (X M, Z M ), it marks the corresponding position of the Mirror Memory. The detector position (X M,Z M ) corresponds to the EM position the position (X M,,T M ) Once a trigger arrives the EM is frozen. Now it contains the analog samples of the charge detected and, in same way, the addresses of the clusters. One has to calculate, for each cluster found, both the fine position x m, relative to a coordinate of the track, adding it to the coarse position given by X M, and the fine position z m, relative to the other one adding it to the coarse position given by Z M. Beside one has to compute the total charge Q produced in the detector by the impinging particle. The valuation of x m, z m and Q can to be performed by a 10-Input Fuzzy Processor (FP). We send, to the FP the 9 data that in the AM form a cross centred in the peak position, and the address T M. We shall apply differente sets of rules to opportune subset of the input to obtain x m, z m and Q. Using the five signals of the column T M, of the AM, from the X M-2 th to the X M+2 th and T M we calculate z m. T M that contains information about the spread, is used to improve the precision. The processor calculates the fine position x m of the centreof-mass (in five bits) referred to anode position X M, along the X direction. So the absolute coding is a word of 14 bits: 9 for the address X M and five for x m. The processor calculates the fine position z m using the five signals of the row X M, from the T M-2 th to the T M+2 th and T M more. The processor calculates z m referred to the Z M position along the z direction. The absolute coding is a word of 13 bits: 8 for the address Z M and 5 for z m. Using the whole set of data we can computes the charge Q in 9 bit. In this way we have a total of 36 Bit/cluster only. All these operations are accomplished for all the clusters. An Output Memory (OM) stores the results of the last event until they are sent to the acquisition system trough a buffer. To accelerate these processes the three operation are made in piping. While one is looking for the position of the peak, already stored in the MM, data are sent from the AM to the FP that is accomplishing computing on the previous data set. The data from the EM are previously coded by a suitable Analog/Digital Converter (ADC). A Control Unit (CU) supervises all the operations. It exchange control signals with triggers and acquisition system. 3. The Transimpedance Amplifier Each anode of the detector is directly bonded to a channel of the TA. Some constraints affect the choice of the amplifier: a small rise time, a good sensitivity, a low noise and, finally, a good margin of phase [4]. Let us remind that, since the TA impulse response is roughly a Gaussian, the output, because of the SDD s Gaussian impulse shape, is a Gaussian too. The 2 2 variance s o of the output signal is σ o = σ t + σ a were s t and s a are the variances of the anode signals and of TA impulse response, respectively. The maximum spread is relative to a particle hitting farthest, e.g. at 35 mm from the anode edge. If this is the case the space spread becomes corresponding to a time spread s t up to 30.8 ns. The peaking time of the TA is imposed by two different and quite opposite demands: one wants to maximise the Signal/Noise (S/N) ratio, but also, to reconstruct easily the centre-of-mass. So it is preferable to not change the input current shape in a remarkable way. This fact suggests to choose a very small rise time. Fig.2. Transimpedance Amplifier schematic diagram Then one can have low gain and instability and noise. But S/N ratio can worsen. A reasonable compromise appears to be a shaping time of 16 ns. Table 1. Preamplifier Main Characteristics channels per chip 32 chips per detector 12 input pitch 210 m average Z =1 mm 63 mv/mip average Z = 35 mm 34 mv/mip sensitivity 2.5 V ns/mip time of impulse response peak corresponding s 18 ns 6 ns minimum s of the output (Z = 1 mm) 6s length 13.3 ns 80 ns average s of the output 6s length 22.8 ns ns maximum s of the output (Z = 35 mm) 6s length 30.8 ns ns output voltage swing 2000 mv Equivalent Noise Charge 300 e - rms dynamic range 512:1 (9 bit) We have developed a solution based on the work presented in [5]. One of the most important problem is the high value of the load capacitance (roughly 10 pf). The schematic diagram of one channel is shown in Fig. 2. The results of the post-layout simulations are in Fig. 3 and 4. The first one shows the output amplitude versus total charge released, for different values of impact point. Fig. 4 is relative to the output shape for two different points of impact and different charges released. Using a Charge Amplifier there is a systematic error depending on Z (up to 10 mm). The TA reduces this error by a factor 10. The most important characteristics of the chip are summarised in Table 1 [6]. 4. The Event Memory Fig.3. Transimpedance Amplifier Amplitude The data coming from the TAs are sent to the EM were several operations are performed. The data are sampled at high speed (25 ns) and stored into the AM to be successively used. In the same time the signals are sent to a CF that looks for clusters, marking theirs posi- Fig. 4. Transimpedance Amplifier Output shapes Fig. 5. AM Schematic diagram tion in the MM. We should use very much hardware to execute Analog/Digital Conversion for all data contained in the AM, consuming a big amount of power. Then we will execute this conversion only for meaningful data that must be read. For the AM we have adopted a solution based on a Switched Capacitor Array (SCA) [7]. It offers several advantages: low cost, dissipation and silicon area, high sampling speed and dynamic range. In Fig. 5 a schematic drawing of AM is shown. We must sample simultaneously data coming from TAs. Therefore we operate per columns, writing into the memory in parallel. Reading is made randomly, Time Peak detector Fig. 7. Cluster Finder Schematic Diagram one cell a time. Therefore only one amplifier per chip is used to read. The control signals are very few for sake of simplicity and to reduce interconnections between the CU and the EM. Inside the chip we have two UP/DOWN Ring Shift Registers (RSRs), one of 256 cells to select a Table 2. Analog Memory main characteristics channels per chip 32 cells per channel 256 cells cells per chip 8192 input voltage swing 2000 mv output voltage swing 2000 mv write frequency 40 MHz read frequency 8 MHz sample and hold time constant 2 ns Dc gain (40 MHz sample rate) 1 Ac gain (10 MHz input signal).98 Input/output recontruction ± 1 mv Power dissipation 1.5 mw/channel column, the other one of 32 to select a row. A very accurate choise of the switches dimentions was performed [8]. The sampling transistor is chosen in such a way to ensure that charge injection is independent on the signal level. The Fig. 6 shows a typical input of the AM together with the output sampled obtained from SPECTRE simulations. Since write and read frequency, are 40 Mhz and 8 Mhz, respectively, the x axis is in period rather than in time. The most important characteristics of the AM are summarised in Table 2. A circuit looks for a time peak in a channel. It is Fig. 6. Typical input and output of the AM Output Signal at maximum of sensitivity Fig. 8. Centre Peak Detector time response a Time Peak Detector (TPD) built around a CR filter and a Zero Crossing Comparator with an exernal controlled trheshold. When a Maximum is detected in a channel, a different circuit, a Centre Peak Detector (CPD) is enabled. It compares this maximum with the signals, at the same time, of the two adjacent channels. In the case it is the highest, a signal is provided to mark a suitable cell of the MM. A schematic diagram of the Cluster Finder is shown in Fig. 7 [9]. The delay between the instant of the maximum and the enable signal provided by the Zero Crossing Detector is less than s. The time response of the CPD is shown in Fig. 8. The lower diagram shows the CPD s output signal in the worst case when the difference among the centre signal and the other ones are minimum [10]. About 8 ns are needs for decision time and other 4 ns are necessary to reset di CPD. Then the CPD works up to 80 MHz. If the CF is too much sensible it may produce ghost tracks. If one fixes the sensitivity to 3 2 times noise no ghost will be detected but about.7% of tracks will be lost. The cells of the MM are addressed by two RSRs, one of 256 unit, to select a column, the other one of 16 to, select a row. The MM is a 256 x 16-bit word RAM. The time to write the whole memory is 6.4 ms. So we will use a very simple binary memory Dynamic RAM but we do not need refresh. 5. The Fuzzy Processor Once the CF detects a cluster we want to determine the two centre-of-mass. Fuzzy Logic is able to Table 3. Fuzzy Processor Main Characteristics n of inputs: 9 from AM, 1 is Z 10 rule memory capacity 20 rules membership functions for each input up to 20 input membership functions shape trapezoidal speed 50 M FIPS n of outputs 4 X or Z output 5 bit single/double output 1 bit charge output 9 bit processing time for each track 1 ms x ENC = 290 e - (4 rules) 20 m z ENC = 290 e - (8 rules) 19 m Q ENC = 290 e - (12 24 % rules) power dissipation 1W solve our problem simply, speedily and sharply. We will start from our previous implemented FP [11]. We decided to use this FP for simpler inferential computational method. Now we dedicate ourselves to enhance the number of inputs and outputs in a short design time. We will use Yager method for inference and defuzzification Fig. 10. Error distribution in of z m measurement and a pipeline architecture with a 50 MHz Clock. Each rule is processed in two Clock periods. We will implement our processor in ES2 CMOS.7m technology. The foreseen characteristics of the Processor are shown in Table 3. Fig. 11. Error in Total Charge measurement 6. Simulation of the Fuzzy Processing Fig. 9. Error distribution in X measurement A lot of simulations have been carried out, for ALICE ITS SDDs using Hijng and Galice [12]. We have used 100,000 hits to obtain a suitable statistic. The signals generated by the simulation were transferred through the TAs and sampled at the LHC rate and stored in the AM. The data obtained were sent to a Rule Generator [13] that has provided the rules for the FP. We have found that FP evaluates the x m with a resolution of about 20 mm (with 290 ENC), using only 4 rules. In the Fig. 9 the distribution of error, in presence of noise, versus anode s displacement is depicted. The antisymmetrical shape of the error depends on the very small numbers of the rules. In the same conditions of noise, the FP evaluates z m with a resolution of about 19 mm, using only 8 rules. In the Fig. 10 the distribution of the error in the evaluation of z m versus Z is shown. We need 12 rules to compute the total charge and we obtain a resolution of about 23%. In Fig. 11 the distribution of the error in the evaluation of Q, versus Q is shown [14]. We are confident that, using a different number of rules, better results can be obtained, especially for Total Charge reconstruction. 7. On Line Calibration Let us inject charges in known points of the detector. Comparing the processed result with the expected ones it is possible, ON-LINE, to correct the rule's parameter to take into account the eventual variations due to temperature or characteristic dispersions. 8. Rate The most pressing conditions for the detector is the centre position of the third ladder. In 1/2 half of this detector we have an average number of 180 hit. Scanning in adequate manner the MM to recall the cluster positions requires about 200 ms. Using a 8 MHz ADC we need about 200 ms too for 180 clusters each for 9 location conversion and transfer. The FP operating at 600 ns ( 12 rulese at 50 ns/rule) requires about 100 ms for processing 180 data. Since we use piping operations the average rate is about 5 KHz. 9. Conclusions FUZZY ON-LINE processing is convenient and feasible. The system requires simple and not expensive hardware. It reduces significantly the number of wires inside the detector itself and toward acquisition system because it possible to put detectors, F.E. and Readout closer. The very fast Fuzzy Processor must put far from the detector in such a way to decrease cabling, power dissipation and matter. The Proposed system produces a significant decrease of the transmitted data, by a factor not less than 400, without loosing essential informations too. It computes, with a reasonable precision, the position of the tracks and the total charge released inside the detector. It lets to correct detector characteristic s dispersions and its temperature drift. The system has a very good noise immunity. References [1] G. V. Russo, C. Petta, D. Lo Presti,, N. Randazzo, M. Russo - 2th Joint Conf. Inf. Sc. Writhsville, N.C., Usa, 28 Sept.-1 Oct. 1995, Proc., pp [2] G. V. Russo, C. Petta, D. Lo Presti, N. Randazzo, M. Russo - Inf.Sc. Ap, Vol 95, n 3/4, Dec 95, [3] N. Antoniu et al. - Tecnical Proposal of ALICE - Cern/LHCC/95-71, Dec [4] W.Sansen - Nucl. Instr. Meth. A253, pp. 427, (1987) [5] P. Jarron, et al. - CERN EPC 95/10, May 1995 [6] N. Randazzo, G. V. Russo, D. Lo Presti, S. Panebianco, C. Petta, S. Reito, M. Russo - 16-Clannels Transimpedence Amplifier for Silicon Drift Detectors - To be Submitted to IEEE Trans VLSi System [7] S. A. Kleinfelder - IEEE Tr-. Nucl. Sci., Vol 37, n 3, pp. 1230, (1990) [8] S. Panebianco, S. Reito, G. V. Russo, D. Lo Presti, C. Petta, N. Randazzo, M. Russo - A 16 Clannels, 256 Cell Analog Memory for Nuclear data Sampling - To be Submitted IEEE Trans Nucl.Sci. [9] C. Caligiore, D. Lo Presti, G. V. Russo, S. Panebianco, C. Petta, N. Randazzo, S. Reito, M. Russo -16 Clannels Cluster Finder for Silicon Drift Detectors - To be submitted to IEEE Tr. Nuc. Sc. [10] D. Lo Presti G. V. Russo, S. Panebianco, C. Petta, N. Randazzo, S. Reito, M. Russo - A Very High Speed and Sensitive 3-Input Peak Detector - To be Submitted to IEEE VLSI Sys.. [11] E. Gandolfi, A. Gabrielli, M. Masetti, M. Russo - App. Comp., Nashville, pp , February 1995 [12] B. Batyunya, A. Zinchenko - Private communication - July 1996 [13] M. Russo - A Genetic Approach to Fuzzy Learning- 1 st Sym. & Work. Neuro-Fu.Sys., Lousanne, Aug [14] C. Petta, M. Russo, G. V. Russo, C. D. Lo Presti, S. Panebianco, N. Randazzo, S. Reito - Off-Line Fuzzy Processing of Data from Silicon Drift Detectors - To be Submitted to N.I.M.
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