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FPGA Design for DDR3 Memory

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sơ đồ khối thiết kế DDR3 contronller, cung cấp kiến thức để thiết kế cho module DDr3 contronller.
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    FPGA Design for DDR3 Memory Sponsored by Teradyne, North Reading, MA A Major Qualifying Project proposal to be submitted to the faculty of Worcester Polytechnic Institute in partial fulfillment of the requirements for the Degree of Bachelor of Science By:  ____________________________________ Laura Fischer  ____________________________________ Yura Pyatnychko Submitted On: 12 March, 2012  ____________________________________ Professor Xinming Huang, Advisor, Electrical & Computer Engineering  ____________________________________ Professor John A. Mcneill, Advisor, Electrical & Computer Engineering  1  Acknowledgements We would like to thank: Teradyne of North Reading, MA , including our contacts, for arranging the project and providing us with the hardware to develop our design. Professor Xinming Huang  for his guidance and advice as an advisor throughout the project. Professor John A. McNeill for organizing the project and attending to the project needs as an advisor.  2  Abstract The project presents a memory arbiter system capable of allowing two systems to communicate to the same DDR3 SDRAM memory. The arbiter was designed using Verilog, implemented using Xilinx Integrated Software Environment (ISE) and validated using iSim and ChipScope. The final design is implemented on a Virtex 6 FPGA chip. The arbiter can achieve a maximum performance of around 50 Gb/s, with the two systems reaching transfer rates of 25 Gb/s.  3 Executive Summary In the last 30 years, computer memory has evolved rapidly, seeing improvements in both capacity and speed. However, the logic for controlling the memory has also become increasingly more complex and difficult to interface with. The third generation of double data rate synchronous dynamic random access memory (DDR3 SDRAM) is the newest and fastest volatile memory currently available. DDR3 DRAM is one of the many types of random access memory used to temporarily hold data that the system (e.g. computer) needs to have quick access to. DRAM memory is designed for communication with a single system. For two systems to share the same memory, an arbiter must be used. The memory arbiter serves as an interface to both systems, and grants each system access to the memory one at a time to avoid collisions. In this project, Teradyne assigned the MQP team the task of developing a memory arbiter for DDR3 SDRAM for implementation on a Virtex 6 FPGA. The DDR3 SDRAM would be used in Teradyne's testers as data buffers between test-benches and the units under tests (UUT). The memory would enable very fast data transfer rates and significantly reduce the time the testers take to transfer data. The development of the arbiter was done on ML605 evaluation kit using Xilinx tools. Xilinx Integrated Software Environment (ISE) served as the primary work-bench for the development of the arbiter. It enabled the team to write Verilog code that describes the design of the arbiter and to insert specialized Xilinx cores, such as a DDR3 memory interface and first in first out (FIFO) blocks. The arbiter was designed to follow a see-saw like data flow. In a two system configuration, one system is given permission to communicate with the arbiter. The permission periodically switches from one system to the other (i.e. switches alternately) regardless of whether either of systems need to send commands. When a system is given permission to the arbiter they are allowed to send read or write commands; these commands are buffered inside FIFOs within the arbiter. When system two is given permission to the arbiter, the arbiter executes the buffered commands of system one by sending them
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